/**
 ******************************************************************************
 * @file    zb32l03x_hal_cortex.h
 * @author  MCU Software Team
 * @Version V1.0.0
 * @Date    2022/01/19
 * @brief   Header file of CORTEX HAL module.
 ******************************************************************************
 **/


#ifndef __ZB32L03x_HAL_CORTEX_H
#define __ZB32L03x_HAL_CORTEX_H

#ifdef __cplusplus
extern "C" {
#endif


#include "zb32l03x_hal_def.h"


/** @addtogroup CORTEX
 * @{
 */

/** @defgroup CORTEX_Exported_Types Cortex Exported Types
 * @{
 */

#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
 * @brief  MPU Region initialization structure
 * @{
 */
typedef struct
{
    uint8_t     Enable;             /*!< Specifies the status of the region.
                                       This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
    uint8_t     Number;             /*!< Specifies the number of the region to protect.
                                       This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
    uint32_t    BaseAddress;        /*!< Specifies the base address of the region to protect.                         */
    uint8_t     Size;               /*!< Specifies the size of the region to protect.
                                       This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
    uint8_t     SubRegionDisable;   /*!< Specifies the number of the subregion protection to disable.
                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
    uint8_t     TypeExtField;       /*!< Specifies the TEX field level.
                                       This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
    uint8_t     AccessPermission;   /*!< Specifies the region access permission type.
                                       This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
    uint8_t     DisableExec;        /*!< Specifies the instruction access status.
                                       This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
    uint8_t     IsShareable;        /*!< Specifies the shareability status of the protected region.
                                       This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
    uint8_t     IsCacheable;        /*!< Specifies the cacheable status of the region protected.
                                       This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
    uint8_t     IsBufferable;       /*!< Specifies the bufferable status of the protected region.
                                       This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
} MPU_Region_InitTypeDef;
/**
 * @}
 */
#endif  /* __MPU_PRESENT */

/**
 * @}
 */



/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
 * @{
 */

/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
 * @{
 */
#define NVIC_PRIORITYGROUP_0         0x00000007U    /*!< 0 bits for pre-emption priority
                                                        4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1         0x00000006U    /*!< 1 bits for pre-emption priority
                                                        3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2         0x00000005U    /*!< 2 bits for pre-emption priority
                                                        2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3         0x00000004U    /*!< 3 bits for pre-emption priority
                                                        1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4         0x00000003U    /*!< 4 bits for pre-emption priority
                                                        0 bits for subpriority */
/**
 * @}
 */

/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
 * @{
 */
#define SYSTICK_CLKSOURCE_HCLK_DIV4    0x00000000U
#define SYSTICK_CLKSOURCE_HCLK         0x00000004U

/**
 * @}
 */

#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
 * @{
 */
#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
#define  MPU_HFNMI_PRIVDEF                (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
 * @{
 */
#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
 * @{
 */
#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
 * @{
 */
#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
 * @{
 */
#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
 * @{
 */
#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
 * @{
 */
#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
 * @{
 */
#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
 * @{
 */
#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
 * @{
 */
#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
/**
 * @}
 */
#endif /* __MPU_PRESENT */

/**
 * @}
 */




/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
 * @{
 */
#define __HAL_CORTEX_SYSTICKCLK_CONFIG      HAL_SYSTICK_CLKSourceConfig
/**
 * @}
 */



/** @addtogroup CORTEX_Exported_Functions
 * @{
 */

/** @addtogroup CORTEX_Exported_Functions_Group1
 * @{
 */
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
 * @}
 */

/** @addtogroup CORTEX_Exported_Functions_Group2
 * @{
 */
/* Peripheral Control functions ***********************************************/
void HAL_NVIC_GetPriority(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);

#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif  /* __MPU_PRESENT */
/**
 * @}
 */

/**
 * @}
 */


/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
 * @{
 */

#define IS_NVIC_PRIORITY_GROUP(GROUP)   (((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                         ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                         ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                         ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                         ((GROUP) == NVIC_PRIORITYGROUP_4))

#define IS_NVIC_PRIORITY(PRIORITY)      ((PRIORITY) < 0x04U)

#define IS_NVIC_DEVICE_IRQ(IRQ)         ((IRQ) >= (IRQn_Type)0x00U)

#define IS_SYSTICK_CLK_SOURCE(SOURCE)   (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                         ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV4))

#if (__MPU_PRESENT == 1U)

#define IS_MPU_REGION_ENABLE(STATE)     (((STATE) == MPU_REGION_ENABLE) || \
                                         ((STATE) == MPU_REGION_DISABLE))

#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

#define IS_MPU_TEX_LEVEL(TYPE)      (((TYPE) == MPU_TEX_LEVEL0)  || \
                                     ((TYPE) == MPU_TEX_LEVEL1)  || \
                                     ((TYPE) == MPU_TEX_LEVEL2))

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
                                         ((NUMBER) == MPU_REGION_NUMBER7))

#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)    ((SUBREGION) < (uint16_t)0x00FF)
#endif  /* __MPU_PRESENT */

/**
 * @}
 */



/**
 * @}
 */


#ifdef __cplusplus
}
#endif

#endif /* __ZB32L03x_HAL_CORTEX_H */
